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CY5057
High-Frequency Flash Programmable PLL Die with Spread Spectrum
Features

Benefits
Flash programmable die for in-package programming of crystal oscillators High resolution phase-locked loop (PLL) with 10-bit multiplier and 7-bit divider Flash programmable capacitor tuning array Simple 2-pin programming interface (excluding VDD and VSS pins) On-chip oscillator used with external 25.1 MHz fundamental tuned crystal Flash programmable spread spectrum with spread percentages between +0.25% and +2.00% Spread spectrum on/off function Operating frequency 5 to 170 MHz at 3.3V 10% Seven-bit linear post divider with divide options from divide-by-2 to divide-by-127 Programmable PD# or OE pin
Enables quick turnaround of custom oscillators and lowers inventory costs through stocking blank parts. In addition, the part may be Flash programmed up to 100 times. This reduces programming errors and provides an easy upgrade path for existing designs. Enables synthesis of highly accurate and stable output clock frequencies with zero or low PPM. Enables fine tuning of output clock frequency by adjusting the CLoad of the crystal. Allows the device to go into standard 4 or 6-pin packages. Lowers cost of oscillator, because PLL may be programmed to a high frequency using a low frequency, low cost crystal. Provides various spread percentage. Provides the ability to enable or disable spread spectrum with an external pin. Provides flexibility in output configurations and testing. Enables low operation or output enable function. Provides flexibility for system applications through selectable instantaneous or synchronous change in outputs. Suitable for most PC, consumer, and networking applications. Has lower EMI than oscillators. Easy to use software support for design entry.

Programmable asynchronous or synchronous OE and PD# modes Low jitter output < 200 ps (pk-pk) at 3.3V 10%

Controlled rise and fall times and output slew rate Software configuration support
Logic Block Diagram
XIN XOUT
Crystal Osc with 8-bit Cap Array 7-bit /Q 10-bit /P Spread Spectrum 100- to 400-MHz PLL 7-bit Output Divider Block
OUT
SSON#
PD#/OE
Flash Configuration/ Spread Spectrum Storage
Cypress Semiconductor Corporation Document #: 38-07363 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 3, 2008
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CY5057
Die Pad Description
Note Active die size: X = 75.0 mils / 1907 m Y = 56.2 mils / 1428 m Scribe: Y (horizontal) = 2.8 mils / 71 m X (vertical) = 3.4 mils / 86.2 m Bond pad opening: 85 m x 85 m Pad pitch: 125 m x 125 m (pad center to pad center) Wafer thickness: 11 mils and 29 mils TYPICAL (See Ordering Information table for details)
Die Pad Summary [Pad coordinates are referenced from the center of the die (X = 0, Y = 0)]
Table 1. Die Pad Summary Name VDD VSS XIN XOUT PD#/OE VPP SDA SSON# 10 Die Pad 1,2 6,7 4 3 5 Power supply Ground Crystal gate pin Crystal drain pin Flash programmable to function as power down or output enable in normal operating mode. Weak pull up is enabled by default Super voltage when going into programming mode Data pin when going into and when in programming mode Active low spread spectrum control. Asserting LOW turns the internal modulation waveform on. Strong pull down is enabled by default. Pull down is disabled in power down mode Clock pin in programming mode. Must be double bonded to the OUT pad for pinouts not using the SSON# function. There is an internal pull down resistor on this pad 9 Clock output. There is an internal pull down resistor on this pad. Weak pull down is enabled by default. Default output is from the reference No connect pin (do not connect this pad) 834.183 462.840 834.183 589.848 Description X Coordinate -843.612 883.743, 887.355 -843.612 -843.612 -843.612 Y Coordinate 597.849, 427.266 -563.304, -369.957 -1.806 236.565 -424.662
SCL
OUT
NC
8
834.183
335.832
Document #: 38-07363 Rev. *E
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CY5057
Functional Description
CY5057 is a Flash programmable, high accuracy, PLL-based die designed for the crystal oscillator market. It also contains spread spectrum circuitry that is enabled or disabled with an external pin. The die is integrated with a low cost 25.1 MHz fundamental tuned crystal in a 4 or 6-pin through hole or surface mount package. The oscillator devices may be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables faster manufacturing of custom and standard crystal oscillators without the need for dedicated and expensive crystals. CY5057 contains an on-chip oscillator and unique oscillator tuning circuit for fine tuning the output frequency. The crystal Cload is selectively adjusted by programming a set of Flash memory bits. This feature is used to compensate for crystal variations or to obtain a more accurate synthesized frequency. CY5057 uses a simple two-pin programming interface excluding the VSS and VDD pins. Clock outputs are generated from 5 MHz to 170 MHz at 3.3V 10% operating voltage. You can reprogram the entire Flash configuration multiple times to alter or reuse the programmed inventory. CY5057 PLL die is designed for very high resolution. It has a 10-bit feedback counter multiplier and a 7-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM error. The output of the PLL or the oscillator is further modified by a 7-bit linear post divider with a total of 126 divider options (2 to 127). CY5057 also contains flexible power management controls. These parts include both power down mode (PD# = 0) and output enable mode (OE = 1). The power down and output enable modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enables CY5057 to have low jitter and accurate outputs. This makes it suitable for most PC, networking, and consumer applications. CY5057 also has an additional spread spectrum feature that is disabled or enabled with an external pin. See Spread Spectrum for details.
PLL Output Frequency
CY5057 contains a high resolution PLL with a 10-bit multiplier and a 7-bit divider. The output frequency of the PLL is determined by the following equation: 2 * ( PBL + 4 ) + Po F PLL = --------------------------------------------- * F REF ( QL + 2 ) In this equation:

Equation (1)
QL is the loaded or programmed reference counter value (Q counter) PBL is the loaded or programmed feedback counter value (P counter) Po is the P offset bit (is only 0 or 1)
In spread spectrum mode, the time averaged P value is used to calculate the average frequency.
Power Management Features
CY5057 contains Flash programmable PD# (active LOW) and OE (active HIGH) functions. If power down mode is selected (PD# = 0), the oscillator and PLL are placed in a low supply current standby mode and the output is tri-stated and weakly pulled low. The oscillator and PLL circuits must relock when the part leaves power down mode. If output enable mode is selected (OE = 0), the output is tri-stated and weakly pulled low. In this mode, the oscillator and PLL circuits continue to operate allowing a rapid return to normal operation when the output is enabled. In addition, the PD# and OE modes may be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the power down or output disable occurs immediately (allowing for logic delays) irrespective of the position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before power down or output enable signal initiated, thus preventing output glitches. In asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of the output.
Flash Configuration and Spread Spectrum Storage Block
Table 2 summarizes the features configurable by the Flash memory bits. Refer to "CY5057 Programming Specification" for programming details. The specification can be obtained from your Cypress factory representative. Table 2. Flash Programmable Features Feedback counter value (P) Reference counter value (Q) Output divider selection Oscillator tuning (load capacitance values) Oscillator direct output Power management mode (OE or PD#) Power management timing (synchronous or asynchronous) Spread spectrum Pull up and Pull down resistors Document #: 38-07363 Rev. *E Adjust Frequency
Spread Spectrum
CY5057 contains spread spectrum with Flash programmable spread percentage and modulation frequency. Center spread nonlinear "hershey kiss" modulation is obtained. Spread percentage is programmed to values between +0.250% and +2.00%, in 0.25% intervals. Only one spread profile (for one specific percentage spread and for one output frequency) may be programmed into the device at a time. CY5057 has a spread spectrum on and off function. The spread spectrum is enabled or disabled through an external pin. Timing this feature is explained in Switching Waveforms on page 7.
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CY5057
Figure 1. Crystal Oscillator Tuning Circuit
RF
XIN
XOUT
CXIN
CXOUT
C7
C6
C5
C4
C3
C2
C1
C0
C0
C1
C2
C3
C4
C5
C6
C7
Table 3. Crystal Oscillator Tuning Cap Values Bit[1] C7 (MSB) C6 C5 C4 C3 C2 C1 C0 (LSB) Capacitance per Bit (pF) 24.32 12.16 6.08 3.04 1.52 0.76 0.38 0.19
Inkless Die Pick Map (DPM) Format
Cypress ships inkless wafers to customers with an accompanying die pick map, which is used to determine the good die for assembly and programming. Customers can also access individual DPM files at their convenience through ftp.cypress.com with a valid user account login and password. Contact your local Cypress Field Application Engineer (FAE) or sales representative for a customer FTP account. The DPM files are named using the fab lot number and wafer number scribed on the wafer. The DPM files are transferred to the customer's FTP account when the factory ships out the wafers against their purchase order (PO).
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply voltage ................................................. -0.5 to +7.0V Input voltage .............................................-0.5V to VDD + 0.5 Storage temperature (non condensing) ...... -55C to +125C Junction temperature................................. -40C to +125C Data retention at Tj = 125C..................................> 10 years Maximum non volatile programming cycles......................100 Static discharge voltage........................................... > 2000V (per MIL-STD-883, method 3015) Output (pad 9) sink or sources current ........20 mA maximum
Note 1. CXIN, CXOUT, and parasitic capacitance due to fixture and package should be included when calculating the total capacitance.
Document #: 38-07363 Rev. *E
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CY5057
Operating Conditions
Parameter VDD TAJ
[2]
Description Supply voltage (3.3V) Operating temperature, junction Maximum capacitive load on the output (CMOS levels spec) VDD = 3.0V to 3.6V, output frequency = 5 MHz to 170 MHz Reference frequency with spread spectrum disabled. Fundamental tuned crystals only Input capacitance (except crystal pins) Crystal input capacitance (all internal caps off) Crystal output capacitance (all internal caps off) Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic)
Min 3.0 -40 -25.1 -10 10 0.005
Max 3.6 100 15 25.1 7 14 14 500
Unit V C pF MHz pF pF pF ms
CLC XREF Cin CXIN CXout TPSRT
DC Electrical Characteristics (Tj = -40 to 100C)
Parameter VIL VIH VOL VOH IILPDOE IIHPDOE IILSR IIHSR IDD IOZ IPD RUP RDN Rf Description Input low voltage PD#/OE and SSON# pins Input high voltage PD#/OE and SSON# pins Output high voltage, CMOS levels Test Conditions CMOS levels, 30% of VDD VDD = 3.0V-3.6V CMOS levels, 70% of VDD VDD = 3.0V-3.6V VDD = 3.0V-3.6V, IOH = -8 mA Min -0.7* VDD 0.4 VDD - 0.4 -------1 80 80 100 -10 10 10 50 50 50 50 6 150 150 -Max 0.3* VDD Unit V V V V A A A A mA A A M k k k
Output low voltage, OUT pin VDD = 3.0V-3.6V, IOL = 8 mA
Input low current, PD#/OE pin VIN = VSS (Internal pull up = 3 M typical) Input high current, PD#/OE pin VIN = VDD (Internal pull up = 100 k typical)
Input low current, SSON# pin VIN = VSS (Internal pull down = 100 k typical) Input high current, SSON# pin Supply current VIN = VDD (Internal pull down = 100 k typical) No load, VDD = 3.0V-3.6V, Fout = 170 MHz
Output leakage current, OUT VDD = 3.0V-3.6V, output disabled with OE pin Standby current Pull up resistor on PD#/OE pin VDD = 3.0V-3.6V, device powered down with PD# VDD = 3.0 to 3.6V, measured at VIN =VSS VDD = 3.0V-3.6V, measured at VIN = 0.7VDD
Pull down resistor on SSON# VDD = 3.0V-3.6V, measured at VIN = 0.5VDD and OUT pins Crystal feedback resistor VDD = 3.0V-3.6V, measured at XIN = 0.
Document #: 38-07363 Rev. *E
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CY5057
AC Electrical Characteristics (Tj = -40 to 100C)
Parameter[2] Fout tr tf DC tJ1 Description Output frequency OUT rise time OUT fall time OUT duty cycle Test Conditions VDD = 3.0 to 3.6V, CL = 15 pF VDD = 3.0V-3.6V, 20% to 80% VDD, CL = 15 pF VDD = 3.0V-3.6V, 80% to 20% VDD, CL = 15 pF Divider output, measured at VDD/2 Crystal direct output, measured at VDD/2 25 MHz < Fout< 133 MHz, VDD/2, SS off Fout< 25 MHz, VDD/2, SS off tJ2 Cycle-to-cycle jitter Fout >133 MHz, VDD/2, SS on 25 MHz < Fout< 133 MHz, VDD/2, SS on Fout< 25 MHz, VDD/2, SS on FMOD DL -R Modulation frequency Crystal drive level Negative resistance Measured at 25.1 MHz, with crystal ESR = 20, cap setting = hex16, DL = program code [1,0] Measured at 25.1 MHz, cap setting = hex 3F 30 ---Min 5 --45 40 -Max 170 2.7 2.7 55 60 200 400 1% of 1/Fout 200 400 1% of 1/Fout 33 540 -200 Unit MHz ns ns % % ps ps s ps ps s kHz W
Peak-to-peak period jitter Fout >133 MHz, VDD/2, SS off
Timing Parameters
Parameter[2] TSSON1 TSSON2 TSSON3 TMOD TSTP,SYNC TSTP,ASYNC TPU,SYNC TPU,ASYNC TPXZ,SYNC TPXZ,ASYNC TPZX,SYNC TPZX,ASYNC TLOCK Description Time from steady state spread to steady state non spread Time from steady state non spread to steady state spread Minimum SSON# pulse width (positive or negative) Spread spectrum modulation period Time from falling edge on PD# to stopped outputs, synchronous mode, T = 1/Fout Time from falling edge on PD# to stopped outputs, asynchronous mode Time from rising edge on PD# to outputs at valid frequency, synchronous mode Time from rising edge on PD# to outputs at valid frequency, asynchronous mode Time from falling edge on OE to high impedance outputs, synchronous mode, T = 1/Fout Time from falling edge on OE to high impedance outputs, asynchronous mode Time from rising edge on OE to running outputs, synchronous mode, T=1/Fout Time from rising edge on OE to running outputs, asynchronous mode PLL lock time (from 0.9 VDD to valid output clock frequency) Min --250 30 ---------Max 600 100 -33.33 1.5T + 350 350 3 3 1.5T+350 350 1.5T + 350 350 10 Unit s s s s ns ns ms ms ns ns ns ns ms
Note 2. In Cypress standard TSSOP packages with external crystal.
Document #: 38-07363 Rev. *E
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CY5057
Switching Waveforms
Figure 2. Duty Cycle Timing (dc)
t1A OUTPUT t1B
t1A Duty = ------- x [ 100% ] t1B
Figure 3. Output Rise/Fall Time
VDD OUTPUT 0V tr tf
Figure 4. Power Down Timing (Synchronous and Asynchronous Modes)
VDD POWER DOWN (PD#) VIL VIH
CLKOUT (synchronous) TSTP CLKOUT (asynchronous)
High Impedance Weakly Pulled Low
TPU
High Impedance Weakly Pulled Low
TPU TSTP
Figure 5. Output Enable Timing (Synchronous and Asynchronous Modes)
VDD OUTPUT ENABLE (OE) VIL VIH
CLKOUT (synchronous) TPXZ CLKOUT (asynchronous)
High Impedance Weakly Pulled Low
TPZX
High Impedance Weakly Pulled Low
TPZX TPXZ
Document #: 38-07363 Rev. *E
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CY5057
Figure 6. Power Up Timing
VDD Power Up 0V 0.9VDD
TPSRT TLOCK
CLKOUT
Valid CLKOUT
Figure 7. Spread Spectrum On and OFF Timing
SSON#
T SSON3 +100% Internal Modulation W aveform T SSON1 T SSON2 0%
-100%
Ordering Information
Ordering Code CY5057-11WAF CY5057-11WAF-IL CY5057-29WAF-IL Active Active Status Obsolete Type Inked wafer (background to 11 mils) Inkless wafer (background to 11 mils) Inkless wafer (thickness 29 mils) Operating Range -40C to 100C -40C to 100C -40C to 100C
Document #: 38-07363 Rev. *E
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CY5057
Document History Page
Document Title: CY5057 High-Frequency Flash Programmable PLL Die with Spread Spectrum Document Number: 38-07363 REV. ** *A ECN 112486 121373 Orig. of Change CKN CKN Submission Date See ECN See ECN New data sheet Added scribe lines to die pad description Added wafer thickness to die pad description Added X and Y coordinates to die pad description Removed list of discrete frequencies and discrete spread percentages Removed references to discrete frequencies and profile tables Replaced with description of software for full programmability Operating frequency changed to 5 MHz-170 MHz Removed C0 and C1 from crystal oscillator tuning circuit; renumbered other capacitors Changed maximum junction temperature to 125C Changed PDOE internal pull up value to 1-6 Mohm when VIN = VSS Changed IILPDOE to 10 A Changed Rf spec to 100 kohm, at condition XIN = 0 Change DL spec to 540 W, at condition cap setting = hex16, DL=10 Added power up timing diagram separate from power down timing diagram Removed die information table Added -11 and other details to ordering Information Added tPU details to operating conditions Changed max TSSON1 value to 600 in timing parameters table Changed parameter TPU under timing parameters to TLOCK with the description "PLL lock time" Altered minimum and maximum values in power up timing figure Modified power down timing diagram Changed power up timing from min. of 50 s to 5 s Added output sink/source current specification in the absolute max ratings Change cap array from 10 to 8-bit Add MSB and LSB in the crystal oscillator tuning cap values table Fixed power up timing diagram Added -R cap setting value FF Added Inkless die information before Absolute Maximum Ratings Added new part number (CY5057-11WAF-IL) with note Updated template. Added Note "Not recommended for new designs." Added part number CY5057K-11WAF-IL in ordering information table. Updated to match data sheet labeled "Rev *C November 16, 2004" (added logo and die number to die drawing; added pull-up & pull-down resistors to features table; revised -R spec and conditions; added missing labels to waveform drawings) Removed CY5057K-11WAF-IL from ordering information table. Updated die dimensions (page 2) with 29mil thickness; corrected scribe variables Description of Change
*B
127414
RGL
See ECN
*C
2143928
FGA/PYRS
See ECN
*D *E
2541797 2600816
AESA KVM/AESA
07/24/08 11/04/08
Document #: 38-07363 Rev. *E
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CY5057
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07363 Rev. *E
Revised November 3, 2008
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